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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">OpenRISC</span></span>

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</style><table class="infobox"><caption class="infobox-title">OpenRISC</caption><tbody><tr><th scope="row" class="infobox-label">Designer</th><td class="infobox-data">Originally Damjan Lampret, now the <a rel="nofollow" class="external text" href="https://openrisc.io/community">OpenRISC Community</a> (Stafford Horne etc.)</td></tr><tr><th scope="row" class="infobox-label">Bits</th><td class="infobox-data"><a href="32-bit" class="mw-redirect" title="32-bit">32-bit</a>, <a href="64-bit" class="mw-redirect" title="64-bit">64-bit</a></td></tr><tr><th scope="row" class="infobox-label">Introduced</th><td class="infobox-data">2000<span style="display:none"> (<span class="bday dtstart published updated">2000</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Version</th><td class="infobox-data">1.4<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label"><a href="Computer_architecture" title="Computer architecture">Design</a></th><td class="infobox-data"><a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></td></tr><tr><th scope="row" class="infobox-label"><a href="Instruction_set" class="mw-redirect" title="Instruction set">Encoding</a></th><td class="infobox-data">Fixed</td></tr><tr><th scope="row" class="infobox-label"><a href="Endianness" title="Endianness">Endianness</a></th><td class="infobox-data">Big; unimplemented stub for Little</td></tr><tr><th scope="row" class="infobox-label">Page size</th><td class="infobox-data">8 KiB</td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data">ORFPX32/64,<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> ORVDX64<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label">Open</th><td class="infobox-data">Yes (LGPL / GPL), hence royalty free</td></tr><tr><th colspan="2" class="infobox-header"><a href="Processor_register" title="Processor register">Registers</a></th></tr><tr><th scope="row" class="infobox-label"><a href="General-purpose_register" class="mw-redirect" title="General-purpose register">General-purpose</a></th><td class="infobox-data">16 or 32</td></tr><tr><th scope="row" class="infobox-label"><a href="Floating_point" class="mw-redirect" title="Floating point">Floating point</a></th><td class="infobox-data">Optional</td></tr></tbody></table>

<p><b>OpenRISC</b> is a project to develop a series of <a href="Open-source_hardware" title="Open-source hardware">open-source hardware</a> based <a href="Central_processing_unit" title="Central processing unit">central processing units</a> (CPUs) on established <a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computer</a> (RISC) principles. It includes an <a href="Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA) using an <a href="Open-source_license" title="Open-source license">open-source license</a>. It is the original flagship project of the <a href="OpenCores" title="OpenCores">OpenCores</a> community.

</p><p>The first (and as of 2019 only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of <a href="32-bit" class="mw-redirect" title="32-bit">32-bit</a> and <a href="64-bit" class="mw-redirect" title="64-bit">64-bit</a> processors with optional <a href="Floating-point_arithmetic" title="Floating-point arithmetic">floating-point arithmetic</a> and <a href="Vector_processor" title="Vector processor">vector processing</a> support.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>

The <a href="OpenRISC_1200" title="OpenRISC 1200">OpenRISC 1200</a> implementation of this specification was designed by Damjan Lampret in 2000, written in the <a href="Verilog" title="Verilog">Verilog</a> <a href="Hardware_description_language" title="Hardware description language">hardware description language</a> (HDL).<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> The later mor1kx implementation, which has some advantages compared to the OR 1200,<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> was designed by Julius Baxter and is also written in Verilog. Software simulators also exist<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> which implement the OR1k specification.

</p><p>The hardware design was released under the <a href="GNU_Lesser_General_Public_License" title="GNU Lesser General Public License">GNU Lesser General Public License</a> (LGPL), while the models and firmware were released under the <a href="GNU_General_Public_License" title="GNU General Public License">GNU General Public License</a> (GPL).

</p><p>A reference <a href="System_on_a_chip" title="System on a chip">system on a chip</a> (SoC) implementation based on the OpenRISC 1200 was developed, named the <i>OpenRISC Reference Platform System-on-Chip</i> (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on <a href="Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate arrays</a> (FPGAs),<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> and there have been several commercial derivatives produced.

</p><p>Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are minSoC, OpTiMSoC and MiSoC.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup>

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<div class="mw-heading mw-heading2"><h2 id="Instruction_set">Instruction set</h2></div>

<p>The instruction set is a reasonably simple traditional RISC architecture reminiscent of <a href="MIPS_architecture" title="MIPS architecture">MIPS</a> using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors.

</p><p>Another notable feature is a rich set of <i>single instruction, multiple data</i> (<a href="SIMD" class="mw-redirect" title="SIMD">SIMD</a>) instructions intended for <a href="Digital_signal_processing" title="Digital signal processing">digital signal processing</a>.

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<div class="mw-heading mw-heading2"><h2 id="Implementations">Implementations</h2></div>

<p>Most implementations are on <a href="Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate arrays</a> (FPGAs) which give the possibility to iterate on the design at the cost of performance.

</p><p>By 2018, the OpenRISC 1000 was considered stable, so ORSoC (owner of OpenCores) began a <a href="Crowdfunding" title="Crowdfunding">crowdfunding</a> project to build a cost-efficient <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuit</a> (ASIC) to get improved performance. ORSoC faced criticism for this from the community. The project did not reach the goal.

</p><p>As of May 2024, no open-source ASIC had been produced.

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<div class="mw-heading mw-heading3"><h3 id="Commercial_implementations">Commercial implementations</h3></div>

<p>Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC and the BA12, BA14, and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE <a href="FPGA_prototyping" title="FPGA prototyping">FPGA prototyping</a> board, which can run both the OpenRISC 1000 and BA12. <a href="Flextronics" class="mw-redirect" title="Flextronics">Flextronics</a> (Flex) and <a href="Jennic_Limited" class="mw-redirect" title="Jennic Limited">Jennic Limited</a> manufactured the OpenRISC as part of an <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuit</a> (ASIC). Samsung uses the OpenRISC 1000 in their DTV system-on-chips (SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series).<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> Allwinner Technology are reported to use an OpenRISC core in their AR100 power controller, which forms part of the A31 ARM-based SoC.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup>

</p><p><a href="Cadence_Design_Systems" title="Cadence Design Systems">Cadence Design Systems</a> have begun using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to <a href="Accellera" title="Accellera">Accellera</a>).<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup>

</p><p><a href="TechEdSat" title="TechEdSat">TechEdSat</a>, the first <a href="NASA" title="NASA">NASA</a> OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup>

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<div class="mw-heading mw-heading3"><h3 id="Academic_and_non-commercial_use">Academic and non-commercial use</h3></div>

<p>Being open source, OpenRISC has proved popular in academic and hobbyist circles. For example, Stefan Wallentowitz<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> and his team at the Institute for Integrated Systems at the <a href="Technische_Universit%C3%A4t_M%C3%BCnchen" class="mw-redirect" title="Technische Universität München">Technische Universität München</a> have used OpenRISC in research into <a href="Multi-core_processor" title="Multi-core processor">multi-core processor</a> architectures.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup>

The <i>Open Source Hardware User Group</i> (OSHUG) in the UK has on two occasions<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> run sessions on OpenRISC, while hobbyist Sven-Åke Andersson has written a comprehensive blog on OpenRISC for beginners,<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> which attracted the interest of <i>Electronic Engineering Times</i> (<a href="EE_Times" title="EE Times">EE Times</a>).<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup>

Sebastian Macke has implemented jor1k, an OpenRISC 1000 emulator in <a href="JavaScript" title="JavaScript">JavaScript</a>, running <a href="Linux" title="Linux">Linux</a> with <a href="X_Window_System" title="X Window System">X Window System</a> and <a href="Wayland_(display_server_protocol)" class="mw-redirect" title="Wayland (display server protocol)">Wayland</a> support.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup>

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<div class="mw-heading mw-heading2"><h2 id="Toolchain_support">Toolchain support</h2></div>

<p>The OpenRISC community have ported the <a href="GNU_toolchain" title="GNU toolchain">GNU toolchain</a> to OpenRISC to support development in the <a href="Programming_language" title="Programming language">programming languages</a> <a href="C_(programming_language)" title="C (programming language)">C</a> and <a href="C%2B%2B" title="C++">C++</a>. Using this toolchain the <a href="Newlib" title="Newlib">newlib</a>, <a href="UClibc" title="UClibc">uClibc</a>, <a href="Musl" title="Musl">musl</a> (as of release 1.1.4), and <a href="Glibc" title="Glibc">glibc</a> libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical <a href="Integrated_development_environment" title="Integrated development environment">integrated development environment</a> (IDE) based on this toolchain. A project to port <a href="LLVM" title="LLVM">LLVM</a> to the OpenRISC 1000 architecture began in early 2012.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup>

</p><p><a href="GNU_Compiler_Collection" title="GNU Compiler Collection">GCC</a> 9 released with OpenRISC support.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup>

</p><p>The OR1K project provides an <a href="Instruction_set_simulator" title="Instruction set simulator">instruction set simulator</a>, or1ksim. The flagship implementation, the OR1200, is a <a href="Register-transfer_level" title="Register-transfer level">register-transfer level</a> (RTL) model in Verilog HDL, from which a <a href="SystemC" title="SystemC">SystemC</a>-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative (see <a href="OVPsim" title="OVPsim">OVPsim</a>), set up by Imperas.

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<div class="mw-heading mw-heading2"><h2 id="Operating_system_support">Operating system support</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Linux_support">Linux support</h3></div>

<p>The mainline <a href="Linux_kernel" title="Linux kernel">Linux kernel</a> gained support for OpenRISC in version 3.1.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup>

The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k).<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> Formerly OpenRISC 1000 architecture, it has been superseded by the mainline port.

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<div class="mw-heading mw-heading3"><h3 id="RTOS_support">RTOS support</h3></div>

<p>Several <a href="Real-time_operating_system" title="Real-time operating system">real-time operating systems</a> (RTOS) have been ported to OpenRISC, including <a href="NuttX" title="NuttX">NuttX</a>, <a href="RTEMS" title="RTEMS">RTEMS</a>, <a href="FreeRTOS" title="FreeRTOS">FreeRTOS</a>, and <a href="ECos" title="ECos">eCos</a>.

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<div class="mw-heading mw-heading2"><h2 id="QEMU_support">QEMU support</h2></div>

<p>Since version 1.2, <a href="QEMU" title="QEMU">QEMU</a> supports emulating OpenRISC platforms.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup>

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<ul><li><a href="Amber_(processor_core)" class="mw-redirect" title="Amber (processor core)">Amber (processor core)</a> – ARM-Compatible OpenCores Project</li>

<li><a href="Free_and_Open_Source_Silicon_Foundation" title="Free and Open Source Silicon Foundation">Free and Open Source Silicon Foundation</a></li>

<li><a href="SuperH#J_Core" title="SuperH">J Core</a> – SuperH-Compatible OpenCores Project</li>

<li><a href="OpenRISC_1200" title="OpenRISC 1200">OpenRISC 1200</a></li>

<li><a href="OVPsim" title="OVPsim">OVPsim</a>, Open Virtual Platforms</li>

<li><a href="OpenSPARC" title="OpenSPARC">OpenSPARC</a> – SPARC-Compatible OpenCores Project</li>

<li><a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://openrisc.io/implementations#mor1kx">"Implementations - OpenRISC"</a>. <i>OpenRisc.io</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2021-04-17</span></span>.</cite></span>

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<li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://openrisc.io/implementations#system-simulators">"Implementations - OpenRISC"</a>. <i>OpenRisc.io</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2021-04-17</span></span>.</cite></span>

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<li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><cite id="CITEREFPelgrimsTierensDriessens2004" class="citation web cs1">Pelgrims, Patrick; Tierens, Tom; Driessens, Dries (2004). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20061127055325/http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf">"Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGAs"</a> <span class="cs1-format">(PDF)</span>. <i>De Nayer Instituut</i>. 1.0. Archived from <a rel="nofollow" class="external text" href="http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2006-11-27<span class="reference-accessdate">. Retrieved <span class="nowrap">2009-03-03</span></span>.</cite></span>

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<li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><cite id="CITEREFLiZuo" class="citation thesis cs1">Li, Xiang; Zuo, Lin. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20111006172138/http://www.olivercamel.com/post/master_thesis.html"><i>Open source embedded platform based on OpenRISC and DE2-70</i></a> (Masters). <a href="KTH_Royal_Institute_of_Technology" title="KTH Royal Institute of Technology">KTH Royal Institute of Technology</a> (KTH), Sweden. Archived from <a rel="nofollow" class="external text" href="http://www.olivercamel.com/post/master_thesis.html">the original</a> on 2011-10-06.</cite>, SoC program</span>

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<li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://openrisc.io/soc">"System-on-Chip - OpenRISC"</a>. <i>OpenRisc.io</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2021-04-17</span></span>.</cite></span>

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<li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://opensource.samsung.com/">Samsung Open Source Release Center</a>, follow the links → TV & VIDEO → TV → DTV → ETC → OR1200.zip</span>

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<li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text">Linux-sunxi project community wiki page on the <a rel="nofollow" class="external text" href="http://linux-sunxi.org/AR100">AR100 controller</a>. Retrieved on 20 July 2013.</span>

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<li id="cite_note-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-13">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.uvmworld.org/uvm-reference-flow.php">UVM Reference Flow</a>, Accellera website (undated).</span>

</li>

<li id="cite_note-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-14">^</a></b></span> <span class="reference-text">Post to the openrisc mailing lists at lists.openrisc.net on 8 April 2012 by Fredrick Bruhn, CEO of ÅAC Microtec</span>

</li>

<li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text"><cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140118171835/http://aacmicrotec.com/index.php/component/content/article/1-news-in-english/111-swedish-breakthrough-in-space-on-nasa-satellite-with-electronics-from-aac-microtec.html">"Swedish breakthrough in space on NASA satellite with electronics from ÅAC Microtec"</a>. <i>ÅAC Microtec</i> (Press release). 2012-10-11. Archived from <a rel="nofollow" class="external text" href="http://www.aacmicrotec.com/index.php/component/content/article/1-news-in-english/111-swedish-breakthrough-in-space-on-nasa-satellite-with-electronics-from-aac-microtec.html">the original</a> on 2014-01-18<span class="reference-accessdate">. Retrieved <span class="nowrap">2018-03-17</span></span>.</cite></span>

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<li id="cite_note-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-16">^</a></b></span> <span class="reference-text"><cite class="citation pressrelease cs1 cs1-prop-foreign-lang-source"><a rel="nofollow" class="external text" href="http://www.aacmicrotec.com/index.php/component/content/article/2-news-in-swedish/112-svenskt-genombrott-i-rymden-pa-nasa-satellit-med-elektronik-fran-aac-microtec.html">"Svenskt genombrott i rymden på NASA-satellit med elektronik från ÅAC Microtec"</a> [Swedish breakthrough in space on NASA satellite with electronics from ÅAC Microtec] (Press release) (in Swedish). 2012-10-11<span class="reference-accessdate">. Retrieved <span class="nowrap">2018-03-16</span></span> – via <a href="Mynewsdesk" title="Mynewsdesk">Mynewsdesk</a>.</cite> <a rel="nofollow" class="external text" href="http://www.mynewsdesk.com/se/uppsala_innovation_centre_ab/pressreleases/svenskt-genombrott-i-rymden-paa-nasa-satellit-med-elektronik-fraan-aaac-microtec-803754">Alt URL</a></span>

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<li id="cite_note-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-17">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130413065707/http://www.lis.ei.tum.de/?id=wallentowitz">"Dipl.-Ing. Dipl.-Wirt.-Ing. Stefan Wallentowitz"</a>. 2009–2013. Archived from <a rel="nofollow" class="external text" href="https://www.lis.ei.tum.de/?id=wallentowitz">the original</a> on 2013-04-13.</cite></span>

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<li id="cite_note-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-18">^</a></b></span> <span class="reference-text"><cite id="CITEREFWallentowitzWildHerkersdorf" class="citation web cs1">Wallentowitz, Stefan; Wild, Thomas; Herkersdorf, Andreas. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130210103934/http://www.lis.ei.tum.de/fileadmin/w00bdv/www/MAPCO/ACACES2010_Poster.pdf">"Multicore Architecture and Programming Model Co-Optimization (MAPCO)"</a> <span class="cs1-format">(PDF)</span> (Research poster at the Sixth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), 11-17 July 2010). Terrassa (Barcelona), Spain. Archived from <a rel="nofollow" class="external text" href="https://www.lis.ei.tum.de/fileadmin/w00bdv/www/MAPCO/ACACES2010_Poster.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 10 February 2013<span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-29</span></span>.</cite></span>

</li>

<li id="cite_note-19"><span class="mw-cite-backlink"><b><a href="#cite_ref-19">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://oshug.org/event/9">Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000)</a>. OSHUG meeting #9, Skills Matter, 116-120 Goswell Road, London, 21 April 2011.</span>

</li>

<li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://oshug.org/event/17">Practical System-on-Chip (Program your own open source FPGA SoC)</a>. OSHUG meeting #17, Centre for Creative Collaboration, 16 Acton Street, London, 29 March 2012.</span>

</li>

<li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.rte.se/blog/blogg-modesty-corex/openrisc-1200-soft-processor">OpenRISC 1200 soft processor</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120513023117/http://www.rte.se/blog/blogg-modesty-corex/openrisc-1200-soft-processor">Archived</a> 2012-05-13 at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a>. Blog post by Sven-Åke Andersson, 2 March 2012.</span>

</li>

<li id="cite_note-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-22">^</a></b></span> <span class="reference-text"><cite id="CITEREFMaxfield2012" class="citation news cs1">Maxfield, Clive (2012-05-03). <a rel="nofollow" class="external text" href="https://www.eetimes.com/author.asp?section_id=14&doc_id=1286116">"Comparing four 32-bit soft processor cores"</a>. <i>Electronic Engineering Times (<a href="EE_Times" title="EE Times">EE Times</a>)</i>. <a href="San_Francisco" title="San Francisco">San Francisco</a>, California, United States: AspenCore Media<span class="reference-accessdate">. Retrieved <span class="nowrap">2019-03-21</span></span>.</cite></span>

</li>

<li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://www.phoronix.com/scan.php?page=news_item&px=MTQ4NDI">OpenRISC Emulator in JavaScript Can Run Wayland</a></span>

</li>

<li id="cite_note-24"><span class="mw-cite-backlink"><b><a href="#cite_ref-24">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://github.com/openrisc/llvm-or1k">"llvm-or1k"</a>. <i>GitHub</i>. 2018-04-06<span class="reference-accessdate">. Retrieved <span class="nowrap">2019-03-21</span></span>.</cite></span>

</li>

<li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://gcc.gnu.org/gcc-9/changes.html#or1k">"GCC 9 changelog"</a>. GNU<span class="reference-accessdate">. Retrieved <span class="nowrap">15 June</span> 2022</span>.</cite></span>

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<li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://archive.today/20120708204051/http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=arch/openrisc;hb=HEAD">"git.kernel.org - linux/kernel/git/torvalds/linux-2.6.git/tree - arch/openrisc/"</a>. git.kernel.org. Archived from <a rel="nofollow" class="external text" href="https://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=arch/openrisc;hb=HEAD">the original</a> on 2012-07-08<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-10-17</span></span>.</cite></span>

</li>

<li id="cite_note-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-27">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://kernelnewbies.org/Linux_3.1#head-37c60fa1253db74ce7d224718a71f5836bd5be09">"Linux 3.1"</a>. <i>Kernel Newbies</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2011-10-17</span></span>.</cite></span>

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<li id="cite_note-28"><span class="mw-cite-backlink"><b><a href="#cite_ref-28">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://wiki.qemu.org/ChangeLog/1.2">QEMU Changelog 1.2</a></span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><span class="official-website"><span class="url"><a rel="nofollow" class="external text" href="http://openrisc.io">Official website</a></span></span></li>

<li><a rel="nofollow" class="external text" href="http://jolt.law.harvard.edu/articles/pdf/v25/25HarvJLTech131.pdf">Open Source Semiconductor Core Licensing, 25 Harvard Journal of Law & Technology 131 (2011)</a> Article analyzing the law, technology and business of open source semiconductor cores</li>

<li><a rel="nofollow" class="external text" href="http://www.beyondsemi.com/">Beyond Semiconductor</a> commercial <a href="Fabless_semiconductor_company" class="mw-redirect" title="Fabless semiconductor company">fabless semiconductor company</a> founded by the developers of OpenRISC</li>

<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070717073636/http://www.dynalith.com/">Dynalith Systems</a> company website.</li>

<li><a rel="nofollow" class="external text" href="http://www.imperas.com/">Imperas</a> company website.</li>

<li><a rel="nofollow" class="external text" href="https://www.flextronics.com/">Flex</a> company website</li>

<li><a rel="nofollow" class="external text" href="http://www.jennic.com/">Jennic</a> company website</li>

<li><a rel="nofollow" class="external text" href="http://www.eetimes.com/story/OEG20000228S0007">Eetimes article</a></li>

<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120513023117/http://www.rte.se/blog/blogg-modesty-corex/openrisc-1200-soft-processor">OpenRISC tutorial</a></li>

<li><a rel="nofollow" class="external text" href="https://github.com/s-macke/jor1k">jor1k</a> on <a href="GitHub" title="GitHub">GitHub</a>, OpenRISC 1000 emulator in JavaScript</li></ul>

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</style><div id="Reduced_instruction_set_computer_(RISC)_architectures114" style="font-size:114%;margin:0 4em"><a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">Reduced instruction set computer</a> (RISC) architectures</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Origins</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Berkeley_RISC" title="Berkeley RISC">Berkeley RISC</a></li>

<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Development<br>active</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Blackfin" title="Blackfin">Analog Devices Blackfin</a></li>

<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a>, <a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li>

<li><a href="Renesas_Electronics" title="Renesas Electronics">Renesas</a> <a href="M32R" title="M32R">M32R</a>, <a href="SuperH" title="SuperH">SuperH</a>, <a href="V850" title="V850">V850</a></li>

<li><a href="SPARC" title="SPARC">SPARC</a></li>

<li><a href="Sunway_(processor)" title="Sunway (processor)">Sunway</a></li>

<li><a href="Unicore" title="Unicore">Unicore</a></li>

<li><a href="Xilinx" title="Xilinx">Xilinx</a> <a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a>, <a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Development<br>discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="DEC_Alpha" title="DEC Alpha">Alpha</a></li>

<li><a href="Apollo_PRISM" title="Apollo PRISM">Apollo PRISM</a></li>

<li><a href="Atmel" title="Atmel">Atmel</a> <a href="AVR32" title="AVR32">AVR32</a></li>

<li><a href="Clipper_architecture" title="Clipper architecture">Clipper</a></li>

<li><a href="AT%26T_Hobbit" title="AT&T Hobbit">CRISP</a></li>

<li><a href="DEC_PRISM" title="DEC PRISM">DEC PRISM</a></li>

<li><a href="Intel_i860" title="Intel i860">Intel i860</a>, <a href="Intel_i960" title="Intel i960">i960</a></li>

<li><a href="Motorola_88000" title="Motorola 88000">Motorola 88000</a>, <a href="M%C2%B7CORE" title="M·CORE">M·CORE</a></li>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Soft_microprocessor23" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Soft_microprocessor23" style="font-size:114%;margin:0 4em"><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a></li>

<li><a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>

<li><a href="Libre-SOC" title="Libre-SOC">Libre-SOC</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li><a href="OpenPower_Microwatt" class="mw-redirect" title="OpenPower Microwatt">OpenPower Microwatt</a></li>

<li><a href="OpenSPARC" title="OpenSPARC">OpenSPARC</a></li>

<li><a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Programmable_logic116" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Programmable_logic116" style="font-size:114%;margin:0 4em"><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Logic_block" title="Logic block">Logic block</a></li></ul></li>

<li><a href="Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a>

<ul><li><a href="Xputer" title="Xputer">Xputer</a></li></ul></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li>

<li><a href="Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li>

<li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Verilog" title="Verilog">Verilog</a>

<li><a href="VHDL-VITAL" class="mw-redirect" title="VHDL-VITAL">VITAL</a></li></ul></li>

<li><a href="SystemVerilog" title="SystemVerilog">SystemVerilog</a>

<li><a href="SystemC" title="SystemC">SystemC</a></li>

<li><a href="Handel-C" title="Handel-C">Handel-C</a></li>

<li><a href="PALASM" title="PALASM">PALASM</a></li>

<li><a href="MyHDL" title="MyHDL">MyHDL</a></li>

<li><a href="Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Accellera" title="Accellera">Accellera</a></li>

<li><a href="Achronix" title="Achronix">Achronix</a></li>

<li><a href="Aldec" title="Aldec">Aldec</a></li>

<li><a href="Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li>

<li><a href="Infineon_Technologies" title="Infineon Technologies">Infineon</a></li>

<li><a href="Intel" title="Intel">Intel</a></li>

<li><a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li>

<li><a href="Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li>

<li><a href="Siemens" title="Siemens">Siemens</a></li>

<li><a href="Synopsys" title="Synopsys">Synopsys</a></li>

<li><a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Stratix" title="Stratix">Stratix</a></li>

<li><a href="Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Intel_Quartus_Prime" class="mw-redirect" title="Intel Quartus Prime">Intel Quartus Prime</a></li>

<li><a href="Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li>

<li><a href="Vivado" title="Vivado">Vivado</a></li>

<li><a href="ModelSim" title="ModelSim">ModelSim</a></li>

<li><a href="List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Intellectual_property" title="Intellectual property">Intellectual<br>property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li>

<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li><a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>

<li><a href="OpenCores" title="OpenCores">OpenCores</a></li>

<li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a>

<ul><li><a href="Libre-SOC" title="Libre-SOC">Libre-SOC</a></li>

<li><a href="OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li>

</div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-06-16" href="https://en.wikipedia.org/wiki/?title=OpenRISC&oldid=1295877831">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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